This commit is contained in:
2026-04-14 14:16:11 +02:00
parent 899c8cffbc
commit 8171cab9cb
5 changed files with 14 additions and 30 deletions

View File

@@ -47,7 +47,6 @@ ADS1256::ADS1256(const int8_t DRDY_pin, const int8_t RESET_pin, const int8_t SYN
// Initialization
void ADS1256::InitializeADC()
{
LOG_DEBUG("Initialize ADC");
// Chip select LOW
CS_LOW();
@@ -77,27 +76,22 @@ void ADS1256::InitializeADC()
_STATUS = 0b00110110; // BUFEN and ACAL enabled, Order is MSB, rest is read only
writeRegister(STATUS_REG, _STATUS);
delay(200);
LOG_DEBUG("Status REG OK");
_MUX = 0b00000001; // MUX AIN0+AIN1
writeRegister(MUX_REG, _MUX);
delay(200);
LOG_DEBUG("Mux REG OK");
_ADCON = 0b00000000; // ADCON - CLK: OFF, SDCS: OFF, PGA = 0 (+/- 5 V)
writeRegister(ADCON_REG, _ADCON);
delay(200);
LOG_DEBUG("Adcon REG OK");
updateConversionParameter();
_DRATE = 0b10000010; // 100SPS
writeRegister(DRATE_REG, _DRATE);
delay(200);
LOG_DEBUG("Drate REG OK");
sendDirectCommand(0b11110000); // Offset and self-gain calibration
LOG_DEBUG("Direct Command OK");
delay(200);
_isAcquisitionRunning = false; // MCU will be waiting to start a continuous acquisition
@@ -131,7 +125,6 @@ void ADS1256::stopConversion() // Sending SDATAC to stop the continuous conversi
void ADS1256::setDRATE(uint8_t drate) // Setting DRATE (sampling frequency)
{
LOG_DEBUG("SetDrate ADC");
writeRegister(DRATE_REG, drate);
_DRATE = drate;
delayMicroseconds(500);
@@ -139,7 +132,6 @@ void ADS1256::setDRATE(uint8_t drate) // Setting DRATE (sampling frequency)
void ADS1256::setMUX(uint8_t mux) // Setting MUX (input channel)
{
LOG_DEBUG("SetMux ADC");
writeRegister(MUX_REG, mux);
_MUX = mux;
// delayMicroseconds(500);
@@ -147,7 +139,6 @@ void ADS1256::setMUX(uint8_t mux) // Setting MUX (input channel)
void ADS1256::setPGA(uint8_t pga) // Setting PGA (input voltage range)
{
LOG_DEBUG("SetPga ADC");
_PGA = pga;
_ADCON = readRegister(ADCON_REG); // Read the most recent value of the register